Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores.
Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores.
It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect.
| CORE0_SET | Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. |
| CORE1_SET | Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. |
| CORE0_CLR | Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. |
| CORE1_CLR | Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. |